One of the test systems for a group of logical circuits in a one-chip microcomputer is a system for inspecting its functions. This is a test system for checking to see whether or not the one-chip microcomputer satisfies specifications assumed by the designer, in which the operation is traced in accordance with its specifications.
As the scale of a one-chip microcomputer becomes greater and complicated, the above-mentioned system for testing functions comes to fail to carry out detections having high failure detection rates, resulting in failure in ensuring sufficient quality. Therefore, a scan test method has generally been used in which memory elements in the circuit are replaced by exclusively-used cells that are connected in a manner analogous to the shift register so that the value setting and reading are carried out with respect to the memory elements in the circuit.
In the above-mentioned scan test method, the exclusively-used cells by which the memory elements are replaced are generally referred to as scan cells, and a plurality of kinds of them exist. For example, in one kind of scan cells, a selector circuit is added to the data input terminal of the memory element.
Here, referring to respective conceptual drawings (FIGS. 12 and 13), an explanation will be given of a group of logical circuits and a scanning test system.
As illustrated in FIG. 12, a group of logical circuits 103 is constituted by memory elements 101 and combination circuits 102. As illustrated in FIG. 8, this scanning test system is classified into memory element sections 203 having only memory elements 202 and combination circuit sections 205 having only combination circuits 204; thus, a group of logical circuits 201 are formed. Then, a test is carried out on the group of logical circuits 201 by repeating two modes, that is, a shift mode and a capture mode.
The switching between the shift mode and the capture mode is carried out by a terminal generally referred to as a test enable terminal which has a function for selecting input data of a selector circuit that is newly added to the scan cell. In other words, the test enable terminal is used so as to effect control as to whether or not the scan cells are connected in a manner analogous to the shift register.
The above-mentioned shift mode is a mode for setting the values of the respective scan cells with the test enable terminal being connected in a manner analogous to the shift register. In contrast, in the capture mode, the test enable terminal is set so as not to be connected in a manner analogous to the shift register, with the result that the combination circuits are operated so that the scan cell is allowed to acquire their values.
Next, referring to FIG. 13, an explanation will be given of the sequence of the scan test.
First, the mode of the group of logical circuits 201 is set in the shift mode by using the test enable terminal so that values required for the test of the combination circuit section 205 are set on all the scan cells. Thereafter, the mode of the group of the logical circuits 201 is switched to the capture mode, and one cycle of a clock signal S206 having a clock cycle is inputted to the scan cells. Then, the mode of the logical circuit group 201 is again switched to the shift mode, and the clock signal S206 is inputted thereto so that the values of the scan cells are successively read, and compared with expected values. Simultaneously, new values required for the next test on the combination circuit section 205 are set on all the scan cells. Thereafter, the tests are carried out by repeating the above-mentioned process.
Here, a test enable signal 208 in FIG. 13 is a signal line connected to the test enable terminal, and the shift mode is set when it goes “High” and the capture mode is set when it goes “Low”. A selector 207 selects the signal from the memory elements 202 when the test enable signal 208 goes “High”, and also selects the signal from the combination circuit 205 when it goes “Low”.
Next, referring to FIG. 14, an explanation will be given on a conventional one-chip microcomputer having an built-in self test function.
A conventional one-chip microcomputer 300 having the built-in self test function is constituted by a memory 301, a CPU 302, a group of logical circuits 303, a pseudo random number generator 304, a logical circuit test compressor 305, a pattern counter 312, a pattern generator 306, a memory test compressor 307, a JTAG circuit 308, a group of exclusively-used test terminals 309 and a group of terminals 310 on specifications. The memory 301, the CPU 302, the group of logical circuits 303 are connected to one another through a bus 311.
A program for controlling the CPU 302 is stored in the memory 301. The group of logical circuits 303 is constituted by circuits that realize specified operations of the one-chip microcomputer 300. The random number generator 304 generates random numbers as test patterns for inspecting the CPU 302 and the group of logical circuits 303, and is formed by, for example, a linear feedback shift register constituted by shift registers having feedbacks. The logical circuit test compressor 305, which compresses values that are outputted on demand by the CPU 302 and the group of logical circuits 303 during the test, is formed by, for example, the above-mentioned linear feedback shift register.
The pattern counter 312, which is used for monitoring the built-in self test while its process is being executed, is constituted by a counter circuit. Here, the pattern counter 312 controls the completions of the operations of the pseudo random number generator 304, the logical circuit test compressor 305, the pattern generator 306 and the memory test compressor 307.
The pattern generator 306 generates test patterns used for inspecting the memory 301. The memory test compressor 307 compresses values that are outputted from the memory 301 on demand during the test, and is formed by, for example, the above-mentioned linear feedback shift register. The JTAG circuit 308 is formed by a circuit conforming to the standard of IEEE 1149.1. In other words, the JTAG circuit 308 is provided with a circuit in which instructions and additional data for the test are read by the constituent elements in series with each other, and from which the data showing the results of the execution of the instruction is read in series with each other. Here, the IEEE 1149.1 is a standard specification in which the standard test terminal specification and test architecture are determined by JTAG (joint test action group).
The group of exclusively-used test terminals 309 is provided with a TDI terminal, TDO terminal, TCK terminal and TMS terminal in accordance with the standard of the IEEE 1149.1. A signal having a clock cycle is inputted to the TCK terminal. A signal for controlling a test operation is inputted to the TMS terminal so that a sampling operation is carried out in synchronism with the signal inputted from the TCK terminal. Instructions and additional data are inputted to the TDI terminal in series with each other so that a sampling operation is carried out in synchronism with the signal inputted from the TCK terminal. Data indicating the results is outputted from the TDO terminal in series with each other, and the alternation of the output value is carried out in synchronism with the signal inputted to the TCK terminal.
The group of terminals 310 on specifications include an input terminal, an output terminal and an input-output terminal based upon the specification of a one-chip microcomputer 300.
The conventional one-chip microcomputer 300 having an built-in self test function is controlled by the group of exclusively-used test terminals 309. In accordance with the instructions and additional data from the group of exclusively-used test terminals 309, the JTAG circuit 308 sets the initial stages of the pseudo random number generator 304, the pattern generator 306, the logical circuit test compressor 305 and the memory test compressor 307, and activates an built-in self test.
When the built-in self test has been activated, a signal generated in the pseudo random number generator 304 is inputted as a test pattern to the CPU 302 and the group of logical circuits 303 which have been allowed to carry out a scan test. Then, data, released from the CPU 302 and the group of logical circuits 303, are compressed by the logical circuit test compressor 305 so that the resulting value is provided as the result of the test of the built-in self test of the CPU 302 and the group of logical circuits 303.
Simultaneously with this, the pattern generator 306 outputs a test pattern to the memory 301, and the data outputted from the memory 301 is compressed by the memory test compressor 307, and the resulting value is provided as the result of the test of the built-in self test of the memory 301.
After the completion of the built-in self test, the operations of the logical circuit test compressor 305 and the memory test compressor 307 are stopped by the pattern counter 312, and in accordance with the instructions and additional data from the group of exclusively-used test terminals 309, the result of the test of the built-in self test of the CPU 302 and the group of logical circuits 303 and the result of the test of the built-in self test of the memory 301 are read out, and compared with expected values outside the one-chip microcomputer 300 so as to make a judgment.
However, in the above-mentioned conventional arrangement, since the one-chip microcomputer having the built-in self test function requires the exclusively-used test terminals, the resulting problem is an increase in the number of the terminals of the one-chip microcomputer.
For example, in the case of IC cards, the number of terminals, coordinate positions and functions and specifications of the terminals are specified by the ISO (International Organization for Standardization) 7816 and the number of terminals are limited to eight. For this reason, even through the built-in self test needs to be carried out, it is not practical to increase the number of exclusively-used test terminals so as to carry out the test.